1. Field of the Invention
The present invention relates to a stepping motor control device capable of reducing the load on a CPU and more particularly, to a stepping motor control device used in an image forming apparatus.
2. Description of the Related Art
In an image forming apparatus, a stepping motor is used as a feeding motor for transporting a sheet in conjunction with image forming. The rotation speed of the stepping motor is controlled by a stepping motor control device. Here, when the rotation speed of the stepping motor is abruptly changed, the stepping motor could be step-out. Therefore, the stepping motor control device is required to control the start and stop of the stepping motor smoothly.
According to a conventional stepping motor control device, one buffer is provided in an ASIC (Application Specific Integrated Circuit). A CPU (Central Processing Unit) writes pulse cycle data that shows a cycle to output a pulse for driving the stepping motor, in the buffer. The ASIC reads the data written in the buffer and outputs the pulse based on the data. The pulse cycle data written in the one buffer is for one step to rotate the stepping motor to a certain angle. In order to start and stop the stepping motor smoothly, data for the plurality of steps are needed.
At this time, when writing of data for one step of the plurality of steps is delayed, for example, the stepping motor cannot be started and stopped smoothly. Therefore, it is necessary to write the data without any delay.
Here, a technique to write data in the plurality of buffers is disclosed in Japanese Unexamined Patent Publication No. 8-149889 and Japanese Unexamined Patent Publication No. 2000-276435.
According to the Japanese Unexamined Patent Publication No. 8-149889, a plurality of buffers is divided into a write target buffer group and a read target buffer group. Data is written while data is read from the read target buffer group. When the data reading from the read target buffer group is completed, the read target buffer and the write target buffer groups are replaced.
Here, the data cannot be written until the data reading from the read target buffer group is completed. In this case, since it is necessary to write the data in the plurality of write target buffers collectively, the load on a CPU is increased and the data writing could be delayed.
According to the Japanese Unexamined Patent Publication No. 2000-276435, a plurality of buffers are divided into a first buffer group in which data outputted from a processor is written and a second buffer group in which data outputted from the first buffer is written. The data writing in the first buffer group is determined based on ON/OFF of a transmission interrupt signal and performed in an interrupt process.
Here, since the data writing is performed in the interrupt process, when the number of the data writing operations is increased, the number of the interrupt processes is increased, so that the load on a CPU is increased.